개념 설명 전체 · v6.18.37 / drivers/clocksource/timer-riscv.c

    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Copyright (C) 2012 Regents of the University of California
    4  * Copyright (C) 2017 SiFive
    5  *
    6  * All RISC-V systems have a timer attached to every hart.  These timers can
    7  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
    8  * setup events, or directly accessed using MMIO registers.
    9  */
   10 
   11 #define pr_fmt(fmt) "riscv-timer: " fmt
   12 
   13 #include <linux/acpi.h>
   14 #include <linux/clocksource.h>
   15 #include <linux/clockchips.h>
   16 #include <linux/cpu.h>
   17 #include <linux/delay.h>
   18 #include <linux/irq.h>
   19 #include <linux/irqdomain.h>
   20 #include <linux/module.h>
   21 #include <linux/sched_clock.h>
   22 #include <linux/io-64-nonatomic-lo-hi.h>
   23 #include <linux/interrupt.h>
   24 #include <linux/of_irq.h>
   25 #include <linux/limits.h>
   26 #include <clocksource/timer-riscv.h>
   27 #include <asm/smp.h>
   28 #include <asm/cpufeature.h>
   29 #include <asm/sbi.h>
   30 #include <asm/timex.h>
   31 
   32 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
   33 static bool riscv_timer_cannot_wake_cpu;
   34 
   35 static void riscv_clock_event_stop(void)
   36 {
   37 	if (static_branch_likely(&riscv_sstc_available)) {
   38 		csr_write(CSR_STIMECMP, ULONG_MAX);
   39 		if (IS_ENABLED(CONFIG_32BIT))
   40 			csr_write(CSR_STIMECMPH, ULONG_MAX);
   41 	} else {
   42 		sbi_set_timer(U64_MAX);
   43 	}
   44 }
   45 
   46 static int riscv_clock_next_event(unsigned long delta,
   47 		struct clock_event_device *ce)
   48 {
   49 	u64 next_tval = get_cycles64() + delta;
   50 
   51 	if (static_branch_likely(&riscv_sstc_available)) {
   52 #if defined(CONFIG_32BIT)
   53 		csr_write(CSR_STIMECMP, ULONG_MAX);
   54 		csr_write(CSR_STIMECMPH, next_tval >> 32);
   55 		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
   56 #else
   57 		csr_write(CSR_STIMECMP, next_tval);
   58 #endif
   59 	} else
   60 		sbi_set_timer(next_tval);
   61 
   62 	return 0;
   63 }
   64 
   65 static int riscv_clock_shutdown(struct clock_event_device *evt)
   66 {
   67 	riscv_clock_event_stop();
   68 	return 0;
   69 }
   70 
   71 static unsigned int riscv_clock_event_irq;
   72 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
   73 	.name			= "riscv_timer_clockevent",
   74 	.features		= CLOCK_EVT_FEAT_ONESHOT,
   75 	.rating			= 100,
   76 	.set_next_event		= riscv_clock_next_event,
   77 	.set_state_shutdown	= riscv_clock_shutdown,
   78 };
   79 
   80 /*
   81  * It is guaranteed that all the timers across all the harts are synchronized
   82  * within one tick of each other, so while this could technically go
   83  * backwards when hopping between CPUs, practically it won't happen.
   84  */
   85 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
   86 {
   87 	return get_cycles64();
   88 }
   89 
   90 static u64 notrace riscv_sched_clock(void)
   91 {
   92 	return get_cycles64();
   93 }
   94 
   95 static struct clocksource riscv_clocksource = {
   96 	.name		= "riscv_clocksource",
   97 	.rating		= 400,
   98 	.mask		= CLOCKSOURCE_MASK(64),
   99 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
  100 	.read		= riscv_clocksource_rdtime,
  101 #if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
  102 	.vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
  103 #else
  104 	.vdso_clock_mode = VDSO_CLOCKMODE_NONE,
  105 #endif
  106 };
  107 
  108 static int riscv_timer_starting_cpu(unsigned int cpu)
  109 {
  110 	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
  111 
  112 	/* Clear timer interrupt */
  113 	riscv_clock_event_stop();
  114 
  115 	ce->cpumask = cpumask_of(cpu);
  116 	ce->irq = riscv_clock_event_irq;
  117 	if (riscv_timer_cannot_wake_cpu)
  118 		ce->features |= CLOCK_EVT_FEAT_C3STOP;
  119 	if (static_branch_likely(&riscv_sstc_available))
  120 		ce->rating = 450;
  121 	clockevents_config_and_register(ce, riscv_timebase, 100, ULONG_MAX);
  122 
  123 	enable_percpu_irq(riscv_clock_event_irq,
  124 			  irq_get_trigger_type(riscv_clock_event_irq));
  125 	return 0;
  126 }
  127 
  128 static int riscv_timer_dying_cpu(unsigned int cpu)
  129 {
  130 	/*
  131 	 * Stop the timer when the cpu is going to be offline otherwise
  132 	 * the timer interrupt may be pending while performing power-down.
  133 	 */
  134 	riscv_clock_event_stop();
  135 	disable_percpu_irq(riscv_clock_event_irq);
  136 
  137 	return 0;
  138 }
  139 
  140 void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
  141 {
  142 	*mult = riscv_clocksource.mult;
  143 	*shift = riscv_clocksource.shift;
  144 }
  145 EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
  146 
  147 /* called directly from the low-level interrupt handler */
  148 static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
  149 {
  150 	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
  151 
  152 	riscv_clock_event_stop();
  153 	evdev->event_handler(evdev);
  154 
  155 	return IRQ_HANDLED;
  156 }
  157 
  158 static int __init riscv_timer_init_common(void)
  159 {
  160 	int error;
  161 	struct irq_domain *domain;
  162 	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
  163 
  164 	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
  165 	if (!domain) {
  166 		pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
  167 		       intc_fwnode);
  168 		return -ENODEV;
  169 	}
  170 
  171 	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
  172 	if (!riscv_clock_event_irq) {
  173 		pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
  174 		return -ENODEV;
  175 	}
  176 
  177 	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
  178 	if (error) {
  179 		pr_err("RISCV timer registration failed [%d]\n", error);
  180 		return error;
  181 	}
  182 
  183 	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
  184 
  185 	error = request_percpu_irq(riscv_clock_event_irq,
  186 				    riscv_timer_interrupt,
  187 				    "riscv-timer", &riscv_clock_event);
  188 	if (error) {
  189 		pr_err("registering percpu irq failed [%d]\n", error);
  190 		return error;
  191 	}
  192 
  193 	if (riscv_isa_extension_available(NULL, SSTC)) {
  194 		pr_info("Timer interrupt in S-mode is available via sstc extension\n");
  195 		static_branch_enable(&riscv_sstc_available);
  196 	}
  197 
  198 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
  199 			 "clockevents/riscv/timer:starting",
  200 			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
  201 	if (error)
  202 		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
  203 		       error);
  204 
  205 	return error;
  206 }
  207 
  208 static int __init riscv_timer_init_dt(struct device_node *n)
  209 {
  210 	int cpuid, error;
  211 	unsigned long hartid;
  212 	struct device_node *child;
  213 
  214 	error = riscv_of_processor_hartid(n, &hartid);
  215 	if (error < 0) {
  216 		pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
  217 			n, hartid);
  218 		return error;
  219 	}
  220 
  221 	cpuid = riscv_hartid_to_cpuid(hartid);
  222 	if (cpuid < 0) {
  223 		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
  224 		return cpuid;
  225 	}
  226 
  227 	if (cpuid != smp_processor_id())
  228 		return 0;
  229 
  230 	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
  231 	if (child) {
  232 		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
  233 					"riscv,timer-cannot-wake-cpu");
  234 		of_node_put(child);
  235 	}
  236 
  237 	return riscv_timer_init_common();
  238 }
  239 
  240 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
  241 
  242 #ifdef CONFIG_ACPI
  243 static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
  244 {
  245 	struct acpi_table_rhct *rhct = (struct acpi_table_rhct *)table;
  246 
  247 	riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU;
  248 
  249 	return riscv_timer_init_common();
  250 }
  251 
  252 TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);
  253 
  254 #endif