Linux v6.18.37 · 원본 파일 · 온라인 원본
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/processor.h
4 *
5 * Copyright (C) 1995-1999 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8#ifndef __ASM_PROCESSOR_H
9#define __ASM_PROCESSOR_H
10
11/*
12 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
13 * no point in shifting all network buffers by 2 bytes just to make some IP
14 * header fields appear aligned in memory, potentially sacrificing some DMA
15 * performance on some platforms.
16 */
17#define NET_IP_ALIGN 0
18
19#define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
20#define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
21
22#define MTE_CTRL_TCF_SYNC (1UL << 16)
23#define MTE_CTRL_TCF_ASYNC (1UL << 17)
24#define MTE_CTRL_TCF_ASYMM (1UL << 18)
25
26#define MTE_CTRL_STORE_ONLY (1UL << 19)
27
28#ifndef __ASSEMBLY__
29
30#include <linux/build_bug.h>
31#include <linux/cache.h>
32#include <linux/init.h>
33#include <linux/stddef.h>
34#include <linux/string.h>
35#include <linux/thread_info.h>
36
37#include <vdso/processor.h>
38
39#include <asm/alternative.h>
40#include <asm/cpufeature.h>
41#include <asm/hw_breakpoint.h>
42#include <asm/kasan.h>
43#include <asm/lse.h>
44#include <asm/pgtable-hwdef.h>
45#include <asm/pointer_auth.h>
46#include <asm/ptrace.h>
47#include <asm/spectre.h>
48#include <asm/types.h>
49
50/*
51 * TASK_SIZE - the maximum size of a user space task.
52 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
53 */
54
55#define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
56#define TASK_SIZE_64 (UL(1) << vabits_actual)
57#define TASK_SIZE_MAX (UL(1) << VA_BITS)
58
59#ifdef CONFIG_COMPAT
60#if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
61/*
62 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
63 * by the compat vectors page.
64 */
65#define TASK_SIZE_32 UL(0x100000000)
66#else
67#define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
68#endif /* CONFIG_ARM64_64K_PAGES */
69#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
70 TASK_SIZE_32 : TASK_SIZE_64)
71#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
72 TASK_SIZE_32 : TASK_SIZE_64)
73#define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
74 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
75#else
76#define TASK_SIZE TASK_SIZE_64
77#define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
78#endif /* CONFIG_COMPAT */
79
80#ifdef CONFIG_ARM64_FORCE_52BIT
81#define STACK_TOP_MAX TASK_SIZE_64
82#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
83#else
84#define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
85#define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
86#endif /* CONFIG_ARM64_FORCE_52BIT */
87
88#ifdef CONFIG_COMPAT
89#define AARCH32_VECTORS_BASE 0xffff0000
90#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
91 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
92#else
93#define STACK_TOP STACK_TOP_MAX
94#endif /* CONFIG_COMPAT */
95
96#ifndef CONFIG_ARM64_FORCE_52BIT
97#define arch_get_mmap_end(addr, len, flags) \
98 (((addr) > DEFAULT_MAP_WINDOW) ? TASK_SIZE : DEFAULT_MAP_WINDOW)
99
100#define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
101 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
102 base)
103#endif /* CONFIG_ARM64_FORCE_52BIT */
104
105extern phys_addr_t arm64_dma_phys_limit;
106#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
107
108struct debug_info {
109#ifdef CONFIG_HAVE_HW_BREAKPOINT
110 /* Have we suspended stepping by a debugger? */
111 int suspended_step;
112 /* Allow breakpoints and watchpoints to be disabled for this thread. */
113 int bps_disabled;
114 int wps_disabled;
115 /* Hardware breakpoints pinned to this task. */
116 struct perf_event *hbp_break[ARM_MAX_BRP];
117 struct perf_event *hbp_watch[ARM_MAX_WRP];
118#endif
119};
120
121enum vec_type {
122 ARM64_VEC_SVE = 0,
123 ARM64_VEC_SME,
124 ARM64_VEC_MAX,
125};
126
127enum fp_type {
128 FP_STATE_CURRENT, /* Save based on current task state. */
129 FP_STATE_FPSIMD,
130 FP_STATE_SVE,
131};
132
133struct cpu_context {
134 unsigned long x19;
135 unsigned long x20;
136 unsigned long x21;
137 unsigned long x22;
138 unsigned long x23;
139 unsigned long x24;
140 unsigned long x25;
141 unsigned long x26;
142 unsigned long x27;
143 unsigned long x28;
144 unsigned long fp;
145 unsigned long sp;
146 unsigned long pc;
147};
148
149struct thread_struct {
150 struct cpu_context cpu_context; /* cpu context */
151
152 /*
153 * Whitelisted fields for hardened usercopy:
154 * Maintainers must ensure manually that this contains no
155 * implicit padding.
156 */
157 struct {
158 unsigned long tp_value; /* TLS register */
159 unsigned long tp2_value;
160 u64 fpmr;
161 unsigned long pad;
162 struct user_fpsimd_state fpsimd_state;
163 } uw;
164
165 enum fp_type fp_type; /* registers FPSIMD or SVE? */
166 unsigned int fpsimd_cpu;
167 void *sve_state; /* SVE registers, if any */
168 void *sme_state; /* ZA and ZT state, if any */
169 unsigned int vl[ARM64_VEC_MAX]; /* vector length */
170 unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */
171 unsigned long fault_address; /* fault info */
172 unsigned long fault_code; /* ESR_EL1 value */
173 struct debug_info debug; /* debugging */
174
175 struct user_fpsimd_state kernel_fpsimd_state;
176 unsigned int kernel_fpsimd_cpu;
177#ifdef CONFIG_ARM64_PTR_AUTH
178 struct ptrauth_keys_user keys_user;
179#ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
180 struct ptrauth_keys_kernel keys_kernel;
181#endif
182#endif
183#ifdef CONFIG_ARM64_MTE
184 u64 mte_ctrl;
185#endif
186 u64 sctlr_user;
187 u64 svcr;
188 u64 tpidr2_el0;
189 u64 por_el0;
190#ifdef CONFIG_ARM64_GCS
191 unsigned int gcs_el0_mode;
192 unsigned int gcs_el0_locked;
193 u64 gcspr_el0;
194 u64 gcs_base;
195 u64 gcs_size;
196#endif
197};
198
199static inline unsigned int thread_get_vl(struct thread_struct *thread,
200 enum vec_type type)
201{
202 return thread->vl[type];
203}
204
205static inline unsigned int thread_get_sve_vl(struct thread_struct *thread)
206{
207 return thread_get_vl(thread, ARM64_VEC_SVE);
208}
209
210static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
211{
212 return thread_get_vl(thread, ARM64_VEC_SME);
213}
214
215static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
216{
217 if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
218 return thread_get_sme_vl(thread);
219 else
220 return thread_get_sve_vl(thread);
221}
222
223unsigned int task_get_vl(const struct task_struct *task, enum vec_type type);
224void task_set_vl(struct task_struct *task, enum vec_type type,
225 unsigned long vl);
226void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
227 unsigned long vl);
228unsigned int task_get_vl_onexec(const struct task_struct *task,
229 enum vec_type type);
230
231static inline unsigned int task_get_sve_vl(const struct task_struct *task)
232{
233 return task_get_vl(task, ARM64_VEC_SVE);
234}
235
236static inline unsigned int task_get_sme_vl(const struct task_struct *task)
237{
238 return task_get_vl(task, ARM64_VEC_SME);
239}
240
241static inline void task_set_sve_vl(struct task_struct *task, unsigned long vl)
242{
243 task_set_vl(task, ARM64_VEC_SVE, vl);
244}
245
246static inline unsigned int task_get_sve_vl_onexec(const struct task_struct *task)
247{
248 return task_get_vl_onexec(task, ARM64_VEC_SVE);
249}
250
251static inline void task_set_sve_vl_onexec(struct task_struct *task,
252 unsigned long vl)
253{
254 task_set_vl_onexec(task, ARM64_VEC_SVE, vl);
255}
256
257#define SCTLR_USER_MASK \
258 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \
259 SCTLR_EL1_TCF0_MASK)
260
261static inline void arch_thread_struct_whitelist(unsigned long *offset,
262 unsigned long *size)
263{
264 /* Verify that there is no padding among the whitelisted fields: */
265 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
266 sizeof_field(struct thread_struct, uw.tp_value) +
267 sizeof_field(struct thread_struct, uw.tp2_value) +
268 sizeof_field(struct thread_struct, uw.fpmr) +
269 sizeof_field(struct thread_struct, uw.pad) +
270 sizeof_field(struct thread_struct, uw.fpsimd_state));
271
272 *offset = offsetof(struct thread_struct, uw);
273 *size = sizeof_field(struct thread_struct, uw);
274}
275
276#ifdef CONFIG_COMPAT
277#define task_user_tls(t) \
278({ \
279 unsigned long *__tls; \
280 if (is_compat_thread(task_thread_info(t))) \
281 __tls = &(t)->thread.uw.tp2_value; \
282 else \
283 __tls = &(t)->thread.uw.tp_value; \
284 __tls; \
285 })
286#else
287#define task_user_tls(t) (&(t)->thread.uw.tp_value)
288#endif
289
290/* Sync TPIDR_EL0 back to thread_struct for current */
291void tls_preserve_current_state(void);
292
293#define INIT_THREAD { \
294 .fpsimd_cpu = NR_CPUS, \
295}
296
297static inline void start_thread_common(struct pt_regs *regs, unsigned long pc,
298 unsigned long pstate)
299{
300 /*
301 * Ensure all GPRs are zeroed, and initialize PC + PSTATE.
302 * The SP (or compat SP) will be initialized later.
303 */
304 regs->user_regs = (struct user_pt_regs) {
305 .pc = pc,
306 .pstate = pstate,
307 };
308
309 /*
310 * To allow the syscalls:sys_exit_execve tracepoint we need to preserve
311 * syscallno, but do not need orig_x0 or the original GPRs.
312 */
313 regs->orig_x0 = 0;
314
315 /*
316 * An exec from a kernel thread won't have an existing PMR value.
317 */
318 if (system_uses_irq_prio_masking())
319 regs->pmr = GIC_PRIO_IRQON;
320
321 /*
322 * The pt_regs::stackframe field must remain valid throughout this
323 * function as a stacktrace can be taken at any time. Any user or
324 * kernel task should have a valid final frame.
325 */
326 WARN_ON_ONCE(regs->stackframe.record.fp != 0);
327 WARN_ON_ONCE(regs->stackframe.record.lr != 0);
328 WARN_ON_ONCE(regs->stackframe.type != FRAME_META_TYPE_FINAL);
329}
330
331static inline void start_thread(struct pt_regs *regs, unsigned long pc,
332 unsigned long sp)
333{
334 start_thread_common(regs, pc, PSR_MODE_EL0t);
335 spectre_v4_enable_task_mitigation(current);
336 regs->sp = sp;
337}
338
339#ifdef CONFIG_COMPAT
340static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
341 unsigned long sp)
342{
343 unsigned long pstate = PSR_AA32_MODE_USR;
344 if (pc & 1)
345 pstate |= PSR_AA32_T_BIT;
346 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
347 pstate |= PSR_AA32_E_BIT;
348
349 start_thread_common(regs, pc, pstate);
350 spectre_v4_enable_task_mitigation(current);
351 regs->compat_sp = sp;
352}
353#endif
354
355static __always_inline bool is_ttbr0_addr(unsigned long addr)
356{
357 /* entry assembly clears tags for TTBR0 addrs */
358 return addr < TASK_SIZE;
359}
360
361static __always_inline bool is_ttbr1_addr(unsigned long addr)
362{
363 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
364 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
365}
366
367/* Forward declaration, a strange C thing */
368struct task_struct;
369
370unsigned long __get_wchan(struct task_struct *p);
371
372void update_sctlr_el1(u64 sctlr);
373
374/* Thread switching */
375extern struct task_struct *cpu_switch_to(struct task_struct *prev,
376 struct task_struct *next);
377
378#define task_pt_regs(p) \
379 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
380
381#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
382#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
383
384/*
385 * Prefetching support
386 */
387#define ARCH_HAS_PREFETCH
388static inline void prefetch(const void *ptr)
389{
390 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
391}
392
393#define ARCH_HAS_PREFETCHW
394static inline void prefetchw(const void *ptr)
395{
396 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
397}
398
399extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
400extern void __init minsigstksz_setup(void);
401
402/*
403 * Not at the top of the file due to a direct #include cycle between
404 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
405 * ensures that contents of processor.h are visible to fpsimd.h even if
406 * processor.h is included first.
407 *
408 * These prctl helpers are the only things in this file that require
409 * fpsimd.h. The core code expects them to be in this header.
410 */
411#include <asm/fpsimd.h>
412
413/* Userspace interface for PR_S[MV]E_{SET,GET}_VL prctl()s: */
414#define SVE_SET_VL(arg) sve_set_current_vl(arg)
415#define SVE_GET_VL() sve_get_current_vl()
416#define SME_SET_VL(arg) sme_set_current_vl(arg)
417#define SME_GET_VL() sme_get_current_vl()
418
419/* PR_PAC_RESET_KEYS prctl */
420#define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
421
422/* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */
423#define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \
424 ptrauth_set_enabled_keys(tsk, keys, enabled)
425#define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
426
427#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
428/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
429long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
430long get_tagged_addr_ctrl(struct task_struct *task);
431#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
432#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
433#endif
434
435int get_tsc_mode(unsigned long adr);
436int set_tsc_mode(unsigned int val);
437#define GET_TSC_CTL(adr) get_tsc_mode((adr))
438#define SET_TSC_CTL(val) set_tsc_mode((val))
439
440#endif /* __ASSEMBLY__ */
441#endif /* __ASM_PROCESSOR_H */